1. Field of the Disclosure
The present disclosure generally relates to electronic circuits and, more particularly, to an electrostatic discharge protection circuit.
2. Brief Description of Related Art
Miniaturization of electronic devices, especially the consumer electronic devices, has been a consistent trend. To meet the demands from the device users to manufacture smaller electronic devices, semiconductor manufacturers have to devise design processes that not only produce compact, yet robust, semiconductor chips to be used in the smaller electronic devices, but also to ensure that the chips are adequately protected from damage by the ever-present electrostatic discharge (ESD). It is observed that short, fast, and high-amplitude ESD pulses are an inevitable part of the day-to-day environment of both chips and the equipment (or electronic device) containing those chips. Hence, ensuring that devices provide a reasonable and acceptable level of tolerance to ESD is an important part of a device design and manufacturing program.
In an integrated circuit (e.g., a CMOS (Complementary Metal Oxide Semiconductor) IC (Integrated Circuit)), the input signals at the IC pins are generally fed to the gates of various transistors connected to relevant input pins. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. For example, the dielectric breakdown strength of silicon dioxide (the material often used to fabricate a transistor's gate) is approximately 8×106 V/cm; thus, a 15 nm gate oxide (i.e., silicon dioxide) will not tolerate voltages greater than 12V without breaking down. Although this is far more than the normal operating voltage of 5V in many IC's, the electrostatic voltages can be significantly higher than the 12 V limit. If such a high voltage is accidentally applied to the pins of an IC package, its discharge (referred to as electrostatic discharge or ESD) can cause breakdown of the gate oxide of the devices to which it is applied.
Therefore, it is desirable to protect all pins of a semiconductor IC (e.g., a CMOS IC) with protective circuits (e.g., ESD protection circuits) to prevent very high electrostatic voltages from damaging MOS gates. These protective circuits are normally placed between the input (or output) pads on the chip and the transistor gates (or circuit portion) connected to the pads. FIG. 1 illustrates a prior art ESD protection circuit 10 placed between an IC pad 12 and a gate (of a transistor (not shown)) or circuit portion to which the pad 12 is connected. The circuit 10 is shown connected between a power supply voltage (Vcc) 16 and a substrate-level voltage (Vss) 18 (which may be held at a circuit ground (GND) potential during IC operation). It is seen from FIG. 1 that the ESD protection circuit 10 includes two diodes 20 (D1) and 22 (D2) connected back-to-back or in series between the Vcc and Vss terminals 16, 18, respectively. A resistor 24 is shown to represent the resistance between the pad 12 and the gate 14 terminals.
In operation, the diodes 20, 22 act as resistors when not conducting. However, when a reverse-bias input voltage (at pad 12) greater than the breakdown voltage of a diode p-n junction is applied, the device D2 (22) operates as a diode (instead of a resistor) and undergoes breakdown. Furthermore, the now-conducting diode D2 will also clamp the negative-going voltage transition at the chip input 12 to one diode drop below the substrate voltage Vss. For example, if the diode drop is 0.7V and Vss=0V, then the input signal will be clamped at −0.7V (=Vss−0.7V). Similarly, the additional protection diode (i.e., diode D1 (20) in FIG. 1) will clamp positive-going input voltage transitions to one diode drop above Vcc. For example, if Vcc =5.0V, then the input signal will be clamped by diode D1 at 5.7V (=Vcc+0.7V).
Thus, it is seen that the ESD protection circuit 10 in FIG. 1 has a shortcoming—i.e., the presence of input signal clamping by the protection diodes 20, 22. In the circuit 10 of FIG. 1, the input signal at pad 12 cannot swing beyond the range of −0.7V (negative 0.7V) to +5.7V because of the reason that if the input is greater than +5.7V, then the upper diode D1 (20) is turned on, and if the input is less than −0.7V (negative 0.7V), then the lower diode D2 (22) is activated. In practice, although the circuit 10 in FIG. 1 protects the transistor gates (or other circuit portions) from high static voltages at the input pads 12, it significantly reduces the operating swing of a non-electrostatic voltage at the input of the IC (not shown). In some applications, the input voltage (which may not be an electrostatic voltage) may itself be higher than Vcc or less than Vss (or GND), but it may not be faithfully conveyed to the circuit portion (connected to the pad 12) because of the clamping function associated with the circuit configuration 10 in FIG. 1. It is therefore desirable to devise an ESD protection circuit that can handle input signal swings greater than the Vcc or less than the circuit GND potential without being turned “on” by the input voltage outside the Vcc-GND range.